The present invention deals with a state machine. More particularly, the present invention deals with a state machine which has adaptable and programmable timing and state generation mechanisms.
State machines are used in a wide variety of applications. Prior state machines typically included two major components. The first component included combinational logic and the second component included an output register. The combinational logic accepted inputs from an input source and provided an output to the output register based on the inputs. The output register was clocked to store the outputs from the combinational logic. The outputs were then fed back into the combinational logic and a new logical output was generated by the combinational logic. This new logical output was then clocked into the output register with the next clock pulse.
With prior state machines, the logical outputs were designed into the combinational logic and were therefore set. In other words, the combinational logic was not programmable to provide different logical output states with the same input signals. Further, the duration of each logical output state was tied directly to the frequency of the clock which clocked the output register. If the clock clocked the output register at an increased speed, yet slowly enough so that the combinational logic could process the new inputs, the duration of each logical output state would decrease as the clock frequency increased. Therefore, if the user of the prior state machine desired that either the logical output states change with certain inputs, or that the duration of each logical output state change, without changing the clock frequency, the combinational logic in the state machine needed to be redesigned. This was very costly and time consuming.
One example of a system in which state machines are generally used, and where adaptability is desirable, is in a computer system. A computer system typically has a number of components or devices. The components are coupled to one another through busses. A bus, along with the particular component or components supported by the bus, are collectively referred to as a bus environment. Various bus environments in a computer system serve as connection points for the components in the system so that the components can communicate with one another, or so that one component can access or manipulate another component.
However, it is common that different components have different communication systems or protocols. Thus, the different components need different bus environments to support them in communication with other components.
As an example, a typical computer system has a processor device (or several processor devices) and input/output (I/O) devices. The processor runs on a processor clock. Therefore, the processor bus environment runs on a time system based on the processor clock. A typical processor bus is defined or specified by the manufacturer or designer of the processor device. For example, the output signals from a processor device step through a certain cycle when performing a read operation on I/O devices. The logical state of the output signals, as well as the timing of those logical states are specified by the manufacturer or designer of the processor device. The processor is typically connected to a processor bus and the I/O devices are typically connected to an I/O bus.
However, the I/O devices are not synchronous with the processor clock and the I/O bus therefore runs on a different time system, other than the processor clock. Further, the logical output states provided by the controller to perform a certain operation may be incompatible, both logically and temporally, with the I/O bus specification. Thus, there is a need to facilitate communication between the processor bus environment and the I/O bus environment so that the processor device can manipulate or communicate with the I/O devices. A circuit which facilitates communication between the two bus environments is typically referred to as a bus interface circuit and utilizes a state machine.
In addition, another aspect of computer systems magnifies the communication problem addressed by a bus interface circuit. Processor specifications have historically been a moving target. In other words, processor designers improve both the functional and speed performance features of the processor with each new generation of processor device. Therefore, with each new generation of processor device, it is typical for a processor bus to have new specifications making the new processor incompatible with previous bus interface circuitry.
Specifically, new processors may contain two types of changes over previous processors. The first is a functional change. If the processor is functionally different than the previous processor, the functional definition of the output signals, or control signals, which are provided from the processor during any given cycle (e.g. a read cycle) are different than they were in the previous generation processor. The output signals simply have different logical output states which define a read cycle. It is evident that such a change requires redesign of the bus interface circuitry responsible for providing the communication link between the processor bus environment and I/O bus environment.
The second type of change which may be made to the processor is a change in the timing or the speed at which the processor operates. It is very common for a new generation of processor to operate at higher speeds than the preceding processor. The problem with such a speed or timing change, in the context of the example in which a processor is coupled to I/O devices such as memory devices, is that the bus interface circuitry is typically designed to optimize the performance of the processor in accessing the I/O devices at the particular speed at which the processor runs. To accomplish this, the bus interface circuitry is typically synchronized with the processor clock. Therefore, when the speed of the processor clock increases or changes, the interface circuitry (if it is even capable of accommodating the faster or slower operation) tracks the processor clock resulting in a corresponding speed or timing change in the output from the bus interface circuitry. Such a change in speed causes the bus interface circuitry to be incompatible with the I/O bus characteristics.
While new generation processors typically change in both speed and function, there are usually no corresponding changes to the I/O bus environment. Unlike the processor bus environment, the I/O bus environment has timing and functional characteristics that do not change (or change quite minimally) over a long period of time. Such a stable I/O bus specification is valuable to the end user of the system because as long as the new generation processors have bus interface circuits which make the new generation processors compatible with the stable I/O bus specification, the end user can upgrade a processor system without incurring the cost of changing all I/O devices. Instead, the end user can use the same I/O devices on a wide variety of processor systems. Such a feature saves expense because the end user can buy I/O devices in greater quantity, the I/O devices can be used in a wide variety of systems, and the I/O devices will not become incompatible with new processor bus environments.
Given the fact that the I/O bus is typically a static design target in that it does not change over many years, and given the fact that the processor bus does change with each new generation of processor, the bus interface circuitry has to change because it is typically synchronously coupled to the processor bus environment. Any significant functional or timing change in the processor therefore renders previous bus interface circuitry, which used prior state machines, unusable with later generation processors. This is true even though the I/O bus specification remains the same.
The reason the bus interface circuitry is relatively inflexible is due to the traditional design of the bus interface circuitry. It is typically designed as a synchronous state machine which specifically relates to the speed of the processor clock and which has a set logic function. Thus, when the speed of the synchronous processor clock changes, the logical and timing operation of the bus interface circuitry changes.
One method used in the past in an attempt to solve the problem of providing communication between the relatively fixed specification for the I/O bus environment and an ever changing processor bus environment was adaptation of functional state machine equations to accommodate several speeds of processor clock and which has a set logical function. However, this task proved to be very complicated. Further, the logical outputs were still specific to the particular clock speeds chosen by the designer. The root of the problem was that in an efficient state machine, no distinction was made between the logical functions which are accomplished and the timing associated with those functions.
In short, simply running the processor clock faster resulted in the outputs provided to the I/O bus from the interface circuitry also being faster. However, the I/O bus control signals are specified with specific timing parameters which are not, in any way, related to the processor clock. By increasing the speed at which the output signals from the bus interface circuitry are provided at the I/O bus, the output signals from the bus interface circuitry move outside the specification of timing parameters for the I/O bus and therefore the interface circuitry becomes incompatible with the I/O bus and needs to be redesigned.
Therefore, there is a need for bus interface circuitry which remains compatible with the I/O bus specifications regardless of the speed at which the processor is operating and regardless of changes in the logical output signals which constitute a processor request. Such a mechanism would save both time and money previously spent in redesigning bus interface circuitry to properly interface the I/O bus environment with the rapidly changing processor bus environment.
Such interface circuitry is but one specific example where a fully adaptable state machine would be useful. A state machine having adaptable logical functions, as well as adaptable timing functions would solve many problems in many different applications.